IEEE Design & Test July/August 2003 Special Features A Practical Methodology for Verifying Pipelined Microarchitectures Ravi Hosabettu, Ganesh Gopalakrishnan, and Mandayam Srivas Solving Satisfiability in Combinational Circuits Joao Marques-Silva and Luis Guerra e Silva Compacting Test Responses for Deeply Embedded SoC Cores Ozgur Sinanoglu and Alex Orailoglu A Hierarchical Infrastructure for SoC Test Management Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, and Yervant Zorian Fault Models and Test Generation for Hardware-Software Covalidation Ian G. Harris Power-Conscious Test Synthesis and Scheduling Nicola Nicolici and Bashir M. Al-Hashimi An Efficient, Low-Cost I/O Subsystem for Network Processors Dionisios N. Pnevmatikatos, Ioannis Sourdis, and Kyriakos Vlachos Departments EIC Message Roundtable Standards Panel Summaries Conference Reports TTTC Newsletter DATC Newsletter The Last Byte ******************** In the next issue of D&T, look for a Special Issue on Speed Test and Speed Binning in DSM Designs, plus a Special ITC Section! --------------------------------------------------- If you wish to be removed from this mailing list, send a message to listserv@computer.org with the following text in the body of the message: unsubscribe dt_subscribers ---------------------------------------------------